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mos integrated circuit m mm m pd16661a 160-output lcd column (segment) driver with ram document no. s11498ej3v0ds00 (3rd edition) date published november 1998 ns cp (k) printed in japan data sheet nec co r po r a t ion 1996,1998 the m pd16661a is a column (segment) driver containing a ram capable of full-dot lcd drive. with 160 outputs, thi s driver has an on-chip display ram of 160 240 2 bits. the driver can be combined with the m pd16666a to display from 1/8 vga to vga (64 0 480 dots). the m pd16661a is upwardly compatible with the m pd16661. features ? display ram incorporated : 160 240 2 bits ? logic voltage : 3.0 to 3.6 v ? duty : 1/240 ? output count : 160 outputs ? capable of gray scale display : 4 gray scales (frame thinning-out) ? memory management : packed pixel system ? 8/16-bit data bus ordering information part number pa ck age m pd16661an- m pd16661an-051 tcp (tab) standard tcp (olb : 0.2 mm-pitch, pliable-output leads) remark the tcp package is custom made, so contact an nec sales representative with your requirements. the information in this document is subject to change without notice. the mar k h h h h shows major revised points. h
2 m m m m pd16661a pin names classification pin name note i/o pad no. function cpu interface d0 to d15 a0 to a16 /cs /oe /we /ube rdy i/o i i i i i o data bus : 16 bits address bus : 17 bits chip select read signal write signal upper byte enable ready signal to cpu (ready state at "h") control signals pl0 pl1 pl2 dir ms bmode gmode /refrh test /reset /doff osc1 osc2 stb /frm l1 l2 /dout i i i i i i i i/o i i i - - i/o i/o i/o i/o o specifies the lsi placement positions (no. 0 to 7) specifies the lsi placement positions (no. 0 to 7) specifies the lsi placement positions (no. 0 to 7) specifies the liquid-crystal panel placement direction master/slave selection pin (master mode at "h") data bus bit selection pin ("h" = 8 bits, "l" = 16 bits) gray scale data weight reverse switching (when data = [1,1], "l" = black, "h" = white) self-diagnosis reset pin (wired-or connection) test pin ("h" = test mode, on-chip pull-down resistor) reset signal display off input signal oscillator externally-attached resistor pin oscillator externally-attached resistor pin column drive signal (ms pin "h" = output, ms pin "l" = input) frame signal (ms pin "h" = output, ms pin "l" = input) row driver drive level selection signal (1st line) row driver drive level selection signal (2nd line) display off output signal liquid-crystal drive y1 to y160 o liquid-crystal drive output power supplies gnd v cc1 v cc2 v 0 v 1 v 2 - - - - - - ground (two pins for v cc1 system , three pins for v cc2 system) 5-v power supply 3.3-v power supply liquid-crystal drive analog power supply liquid-crystal drive analog power supply liquid-crystal drive analog power supply note 3.3-v pin : d0 to d15, a0 to a16, /cs, /oe, /we, /ube, rdy, bmode, gmode, pl0, pl1, pl2, dir, osc1, osc2, /reset, /doff, test, ms 5-v pin : stb, /frm, l1, l2, /dout remark /xxx indicates active low signal. 3.3 v 3.3 v 5.0 v h
3 m m m m pd16661a block diagram dir pl0,1,2 test a0 to a16 rdy control /cs,/oe, /we,/ube bmode gmode /refrh d0 to d15 /doff 3.3 v operation 5.0v operation 3.3 v operation 5.0 v operation /frm stb /dout l1 l2 y1 y2 y3 y160 dec arbiter address management circuit stop data latch(2) frc control data latch(1) ram 160x240x2 bits v 0 v 1 v 2 /reset ms osc1 osc2 internal timing generation liquid-crystal timing generation /frm stb liquid-crystal drive circuit 160 outputs level shifter self-diagnosis circuit cr oscillator address input control data bus control frame thinning-out
4 m m m m pd16661a 1. block functions (1) address management circuit the address management circuit converts the addresses transferred from the system via a0 to a16 into addresses compatible with the memory map of the on-chip ram. this function can be used to address up to vga size (480 640 dots) with 8 of these lsis, thus making it possible to configure a liquid-crystal display system without difficulty. (2) arbiter the arbiter adjusts the contention between the ram access from the system and the ram read on the liquid- crystal drive side. (3) ram static ram (single port) of 160 240 2 bits (4) data bus control the data bus controls the data transfer directions by means of read/write from the system. the mode can be switched from 8 bits to 16 bits by the bmode pin, and the relation between the display data and the gray scale can be switched by the gmode pin. (5) frame thinning-out control the frame thinning-out control indicates the four gray scales with three thinning-out frames. the thinning-out method can be changed in units of 9 pixels (3 columns 3 lines). (6) internal timing generation the internal timing to each block is generated from the /frm and stb signals. (7) cr oscillator in master mode, this oscillator generates the clock that is the reference for the frame frequency. the frame frequency is one 484th (1/484) of this oscillation. for example, if the frame frequency is 80 hz, an oscillation frequency of 38.72 khz is necessary. as the cr has a built-in capacitance, adjust the required oscillation frequency with an externally attached resistor. in slave mode, oscillation is stopped. (8) liquid-crystal timing generation in master mode, /frm (the frame signal) and stb (the column drive signal strobe) are generated. (9) frc control this circuit realizes the four gray-scale displays.
5 m m m m pd16661a (10) data latch (1) this data latch reads and latches 160-pixel data from the ram. (11) data latch (2) this data latch synchronizes with the stb signal and latches 160-pixel data. (12) level shifter the level shifter converts the voltage from the operating voltage of the internal circuit (3.3 v) to the voltage of the liquid-crystal drive circuit and row driver interface (5.0 v). (13) dec the dec decodes the gray scale display data to make it compatible with the liquid-crystal drive voltages v0, v1, and v2. (14) liquid-crystal drive circuit this circuit selects one of the display off signal (/doff)-compatible liquid-crystal drive power supplies v0, v1, or v2, and generates the liquid-crystal applied voltage. (15) self-diagnosis circuit this circuit automatically detects any occurrence of an operation timing lag between the master chip and the slave chip that has been caused by outside noise, and sends a refresh signal to all the column drivers. 2. memory map address a16 a0 description 00000h : : display data of nos. 0, 2, 4, and 6 0f000h : : display data of nos. 1, 3, 5, and 7 1d f a 0 h : 1ffffh unused
6 m m m m pd16661a address map image diagram (example of vga-size configuration) column direction specified with a7 to a0 line direction specified with a16 to a8 y1 y1 y1 y1 y160 y160 y160 y160 y1 y1 y1 y1 y160 y160 y160 y160 no.0 no.2 no.4 no.6 no.1 no.3 no.5 no.7 address setting direction address setting direction l1 l1 l240 l240
7 m m m m pd16661a 3. data buses the method for lining up byte data on the data bus line is essentially the little endian system adopted by nec and intel corp. 3.1 16-bit data bus (bmode = l) byte unit access d0 to d7 d8 to d15 00000h 00001h 00002h 00003h 00004h 00005h :: :: word unit access d0 to d7 d8 to d15 00000h 00002h 00004h : : for access from the system to be performed in word units (16 bits), or byte units (8 bits), /ube (upper-byte enable) and a0 are used to show whether valid data is in the bytes of either (or both) d0 to d7 or d8 to d15. i/o /cs /oe /we /ube a0 mode d0 to d7 d8 to d15 hxxxxnot selectedhi-z hi-z llhl l h l h l read dout hi-z dout dout dout hi-z lhl l l h l h l write din x din din din x l l h x h x x h x h output disable hi-z hi-z hi-z hi-z remark x : dont care, hi-z : high impedance the address setting direction ? is as shown on the right. the address setting direction ? is as shown on the right.
8 m m m m pd16661a 3.2 8-bit data bus (bmode = h) d0 to d7 00000h 00001h 00002h : : i/o /cs /oe /we mode d0 to d7 d8 to d15 h x x not selected hi-z note l l h read dout note lhlwrite din note l h h output disable hi-z note note when bmode = h, d8 to d15 and /ube are pulled down internally, so either leave them open, or connect them to the gnd. remark x : dont care, hi-z : high impedance the address setting direction ? is as shown on the right.
9 m m m m pd16661a 4. relationship between data bits and pixels because the display is in four gray scales, each pixel consists of two bits. the ram is configured with four pixels (8 pixels per word) using the packed pixel system. (1) bmode = l in byte unit access (8 bits) d0 d1 pixel 1 d2 d3 pixel 2 d4 d5 pixel 3 d6 d7 pixel 4 d8 d9 pixel 5 d10 d11 pixel 6 d12 d13 pixel 7 d14 d15 pixel 8 ? ? ? ? ? ? ? ? ? y ? ? ? ? ? ? ? ? ? t ? ? ? ? ? ? ? ? ? y ? ? ? ? ? ? ? ? ? t 0 0 0 0 0 h 0 0 0 0 1 h pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 pixel 8 ? ? ? y ? ? ? t 0 0 0 0 0 h ? ? ? y ? ? ? t 0 0 0 0 1 h ? ? ? y ? ? ? t 0 0 0 0 2 h ? ? ? y ? ? ? t 0 0 0 0 3 h liquid-crystal panel pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 pixel 8 in word unit access (16 bits) d0 d1 pixel 1 d2 d3 pixel 2 d4 d5 pixel 3 d6 d7 pixel 4 d8 d9 pixel 5 d10 d11 pixel 6 d12 d13 pixel 7 d14 d15 pixel 8 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? y ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? t 0 0 0 0 0 h pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 pixel 8 liquid-crystal panel pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 pixel 8 ? ? ? ? ? ? ? ? y ? ? ? ? ? ? ? ? t ? ? ? ? ? ? ? ? y ? ? ? ? ? ? ? ? t 0 0 0 0 0 h 0 0 0 0 2 h (2) bmode = h d0 d1 pixel 1 d2 d3 pixel 2 d4 d5 pixel 3 d6 d7 pixel 4 d0 d1 pixel 5 d2 d3 pixel 6 d4 d5 pixel 7 d6 d7 pixel 8 ? ? ? ? ? ? ? ? ? y ? ? ? ? ? ? ? ? ? t ? ? ? ? ? ? ? ? ? y ? ? ? ? ? ? ? ? ? t 0 0 0 0 0 h 0 0 0 0 1 h liquid-crystal panel pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 pixel 8 ? ? ? y ? ? ? t 0 0 0 0 0 h ? ? ? y ? ? ? t 0 0 0 0 1 h ? ? ? y ? ? ? t 0 0 0 0 2 h ? ? ? y ? ? ? t 0 0 0 0 3 h pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 pixel 8
10 m m m m pd16661a 5. relationship between display data and gray-scale level (1) gmode = l d n d n+1 gray scale level display state liquid-crystal state 000 off display 101 off state 012 113 on (2) gmode = h d n d n+1 gray scale level display state liquid-crystal state 113 off display 012 off state 101 000 on
11 m m m m pd16661a 6. lsi placement and address management addresses can be managed to allow the use of a maximum of eight m pd16661a devices for configuring a liquid- crystal display of up to vga size (480 640 dots). up to eight of these lsis can be connected to the same data bus and to the /cs, /we, and /oe pins, which are shared. one screen of the liquid-crystal display can be treated as one memory area in the system, so it is not necessary to decode more than one m pd16661a device. the pl0, pl1, and pl2 pins are used to specify the lsi no. and determine the lsi placement. the dir pin is used to determine the direction (perpendicular, lateral) of the liquid-crystal display. pl2 pl1 pl0 lsi no. 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 no. 0 no. 1 no. 2 no. 3 no. 4 no. 5 no. 6 no. 7
12 m m m m pd16661a landscape vga size address dir = 0 00000 y1 00100 0ee00 0ef00 0f000 0f100 1de00 1df00 00026 00126 0ee26 0ef26 0f026 0f126 1de26 1df26 00028 00128 0ee28 0ef28 0f028 0f128 1de28 1df28 0004e 0014e 0ee4e 0ef4e 0f04e 0f14e 1de4e 1df4e 00050 00150 0ee50 0ef50 0f050 0f150 1de50 1df50 00076 00176 0ee76 0ef76 0f076 0f176 1de76 1df76 00078 00178 0ee78 0ef78 0f078 0f178 1de78 1df78 0009e 0019e 0ee9e 0ef9e 0f09e 0f19e 1de9e 1df9e y153 y8 y160 y153 y1 y160 y1 y8 y153 y160 y1 y8 y153 y160 y8 y153 y160 y1 y8 no.0 no.2 no.4 no.6 no.1 no.3 no.5 no.7 l1 l2 l239 l240 l1 l2 l239 l240 y153 y160 y1 y8 y153 y160 y1 y8 y1 y8 y153 y160 specified with a7 to a0 specified with a16 to a8
13 m m m m pd16661a portrait vga size address dir = 1 00000 specified with a16 to a8 00100 0ee00 0ef00 0f000 0f100 1de00 1df00 00026 00126 0ef26 0ef26 0f026 0f126 1de26 1df26 00028 00128 0ee28 0ef28 0f028 0f128 1de28 1df28 0004e 0014e 0ee4e 0ef4e 0f04e 0f14e 1de4e 1df4e 00050 00150 0ee50 0ef50 0f050 0f150 1de50 1df50 00076 00176 0ee76 0ef76 0f076 0f176 1de76 1df76 00078 00178 0ee78 0ef78 0f078 0f178 1de78 1df78 0009e 0019e 0ee9e 0ef9e 0f09e 0f19e 1de9e 1df9e no.0 no.2 no.4 no.6 no.1 no.3 no.5 no.7 l1 l2 l239 l240 l1 l2 l239 l240 y153 y160 y1 y8 y153 y160 y1 y8 y153 y160 y1 y8 y153 y160 y1 y8 y1 y8 y160 y153 y1 y8 y160 y153 y1 y8 y160 y153 y1 y8 y160 y153 specified with a7 to a0
14 m m m m pd16661a 7. cpu interface 7.1 function of the rdy (ready) pin the on-chip ram uses a single-port ram. in order to avoid conflict between accessing from the cpu side and reading on the liquid-crystal drive side, the rdy pin performs a wait operation on the cpu. (1) timing (2) connection of the rdy pin the rdy pin uses a 3-state buffer. externally attach a pull-up resistor to the rdy pin. when more than one m pd16661a is used, wired-or connect each lsi rdy pin. hi-z wait ready hi-z a0 to a16,/ube /cs /oe,/we rdy wait cpu rdy column driver rdy ready input pull-up resistor column driver v cc2 h
15 m m m m pd16661a 7.2 access timing (1) display data read timing (2) display data write timing a16 to a0 d15 to d0 /ube /cs /oe rdy hi-z hi-z hi-z hi-z dout a16 to a0 d15 to d0 /ube /cs /we rdy hi-z hi-z din h
16 m m m m pd16661a 8. gray scale control the four gray scales are expressed in terms of 3 thinning-out frames. the thinning-out method is changed by 9 pixels: pixel numbers 1, 2, and 3, and line numbers 1, 2, and 3 of the liquid-crystal panel. frame thinning-out method 1 1 2 gray scale 0 2 frame 1 3 1 2 frame 2 3 1 2 frame 3 3 column 3 1 2 3 1 2 3 1 2 3 gray scale 1 gray scale 2 gray scale 3 line
17 m m m m pd16661a 9. liquid-crystal timing generation 9.1 reset state in the reset state, the internal counter is zero-cleared. after the reset is released, the display off function operates during the 4-frame cycle, even if the /doff pin is at h. 9.2 liquid-crystal timing generation circuit when the master mode is set with ms = h, this circuit generates the signals /frm and stb at a duty ratio timing of 1/240. it also generates l1 and l2, which are the drive voltage selection signals for the row driver. the /frm signal is generated twice per frame. the stb signal is generated 121 times per half frame, or 242 times per frame. generation of /frm & stb signals generation of l1 and l2 signals stb 1 2 3 4 1234 1234 1234 l1 1111 1111 0000 0000 l2 1010 0101 0101 1010 /reset /frm /dout internal state display off display on 123456 osc1 /frm stb 121 1 121 frame 1 121 1 2 2 2
18 m m m m pd16661a 10. self-diagnosis function this is a function to check whether or not there has been a delay in the operation timing of each column driver caused by external noise, etc. the slave chip compares the l1 and l2 signals of the master chip with the l1 and l2 signals generated internally, and if a mismatch is discovered, the slave chip sends a refresh signal to all the column drivers. when the refresh signal is received, the internal reset is activated, and the timing is initialized. at this time, the display turns off while /refrh = l and during the four frame cycle. the l1 and l2 signals are checked for mismatch at the rising edge of /frm once every half frame. block configuration diagram (slave side) l1(master) l2 (master) l1 (slave) l2 (slave) /refrh initialized mismatch initialized mismatch /reset /refrh l1 l2 internal reset internal l1 signal internal l2 signal self-diagnosis circuit
19 m m m m pd16661a 11. system configuration example this is an example of the configuration of a liquid-crystal panel of half vga size (480 320, perpendicular) using four m pd16661a devices and two row drivers. each column driver sets the lsi no. with the pl0, pl1, and pl2 pins. the dir pin of each column driver is set to low. one of the column drivers only is set to master; all the others are set to slave. signals are supplied from the master column driver to the slave column drivers and the row drivers. the osc1 and osc2 pins have an oscillator resistor attached on the master, and are left open on the slaves. all the signals from the system side (d0 to d15, a0 to a16, /cs, /oe, /we, /ube, rdy, /reset, /doff) are connected in parallel to the column driver. a pull-up resistor is attached to the rdy signal. the test pin is used to test the lsi, and is left open or connected to the gnd when the system is configured. rdy /doff /reset d0 to d15 a0 to a16 control ( /cs, /oe, /we, /ube) master no.0 slave no.1 slave no.3 row driver row driver slave no.2 y1 y160 y160 y1 y160 y1 y1 y160 240 240 stb /frm /dout,/doff' l1 l2 osc2 osc1 v cc2 /refrh scan direction scan direction remark /doff is an input pin of row driver.
20 m m m m pd16661a 12. chip set power supply input sequence it is recommended that the power supply be input in the following way. v cc2 ? v cc1 ? input ? v dd , v ee ? v 1 , v 2 make sure that the lcd drive voltages are input last. notes 1. inputting the selection pins (pl0, pl1, pl2, dir, ms, bmode) at the same time as the v cc2 pin is unproblematic. 2. it is not necessary to turn on v dd and v ee at the same time. v dd and v ee are the liquid-crystal power supplies of the row driver. caution disconnection of the chip set power supply is done in the reverse order of the input sequence. v cc2 v cc1 v dd v ee v 1 v 2 /reset off off off off off off 0 v 0 v on on on on on on 4.5 v 0.3 v cc2 at least 0 s cpu interface (a0 to a16, /cs, /oe, /we, /ube,d0 to d15, /doff) note2 note2 note1 3.3 v 3.3 v at least 0 s at least 100 ns at least 0 s h
21 m m m m pd16661a 13. example of the configuration of the module - - - - internal schottky barrier diode for power supply protection reinforcement note v dd and v ee are the liquid-crystal power supplies of the row driver. remark use the schottky barrier diode at v f = 0.5 v or less. v dd v cc1 v 2 v 1 v 0 v ss v ee note note configure the diodes that are enclosed in the dotted lines when v0 is not 0 v (gnd). h
22 m m m m pd16661a 14. electrical characteristics absolute maximum ratings (t a = +25 c) parameter symbol ratings unit remark supply voltage (1) v cc1 - 0.5 to +6.5 v note1 supply voltage (2) v cc2 - 0.5 to +4.5 v note2 input /output voltage (1) v i/o1 - 0.5 to v cc1 + 0.5 v note1 input /output voltage (2) v i/o2 - 0.5 to v cc2 + 0.5 v note2 input/ output voltage (3) v i/o3 - 0.5 to v cc1 + 0.5 v note3, note4 operating ambient temperature t a - 20 to +70 c storage temperature t stg - 40 to +125 c notes1. 5-v signals (/frm, stb, /dout, l1, l2) 2. 3.3-v signals (ms, dir, pl0 to pl2, a0 to a16, /cs, /oe, /we, /ube, rdy, d0 to d15, /reset, osc1, osc2, /doff, test, gmode, bmode, /refrh) 3. liquid-crystal drive power supplies (v 0 , v 1 , v 2 , y1 to y160) 4. set v 0 < v 1 < v 2 caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating range (t a = - - - - 20 to +70 c, v 0 = 0 v) parameter symbol min. typ. max. unit remark supply voltage (1) v cc1 4.5 5.0 5.5 v supply voltage (2) v cc2 3.0 3.3 3.6 v input voltage (1) v i1 0v cc1 v note1 input voltage (2) v i2 0v cc2 v note2 v 1 input voltage v 1 v 0 v 2 v v 2 input voltage v 2 v 1 v cc1 v osc external resistor r osc 300 700 k w notes1. 5-v signals (/frm, stb) 2. 3.3-v signals (ms, dir, pl0 to pl2, a0 to a16, /cs, /oe, /we, /ube, rdy, d0 tod15, /reset, osc1, osc2, /doff, test, gmode, bmode, /refrh)
23 m m m m pd16661a dc characteristics (unless otherwise specified, v cc1 = 4.5 to 5.5 v, v cc2 = 3.0 to 3.6 v, v 0 = 0 v, v 1 = 1.4 to 2.0 v, v 2 = 2.8 to 4.0 v, t a = - - - - 20 to +70 c) parameter symbol min. typ. max. unit remark high-level input voltage (1) v cc1 v ih1 0.7 v cc1 v note1 low-level input voltage (1) v cc1 v il1 0.3 v cc1 v note1 high-level input voltage (2) v cc2 v ih2 0.7 v cc2 v note2 low-level input voltage (2) v cc2 v il2 0.3 v cc2 v note2 high-level input voltage (2) v cc2 v ih3 0.8 v cc2 v note4 low-level input voltage (2) v cc2 v il3 0.2 v cc2 v note4 high-level output voltage (1) v cc1 v oh1 v cc1 - 0.4 vi oh = - 1 ma, note3 low-level output voltage (1) v cc1 v ol1 0.4 v i ol = 2 ma, note3 high-level output voltage (2) v cc1 v oh2 v cc1 - 0.4 vi oh = - 2 ma, note1 low-level output voltage (2) v cc1 v ol2 0.4 v i ol = 4 ma, note1 high-level output voltage (3) v cc2 v oh3 v cc2 - 0.4 vi oh = - 1 ma, note4 low-level output voltage (3) v cc2 v ol3 0.4 v i ol = 2 ma, note4 input leakage current (1) i i1 10 m a other than test pin, v i = v cc2 or gnd input leakage current (2) i i2 10 40 100 m a pull-down (test pin), v i = v cc2 current consumption for display operation (1) i mas1 40 m amaster, v cc1 , note5 current consumption for display operation (2) i mas2 150 m amaster, v cc2 , note5 current consumption for display operation (3) i slv1 30 m aslave, v cc1 , note5 current consumption for display operation (4) i slv2 100 m aslave, v cc2 , note5 liquid-crystal driving output on resistance r on 12k w note6 notes 1. 5-v signals (/frm, stb,l1,l2) 2. 3.3-v signals (ms, dir, pl0 to pl2, a0 to a16, /cs, /oe, /we, /ube, rdy, d0 to d15, /reset, /doff, test, gmode, bmode) 3. /dout pin 4. d0 to d15, rdy, and osc2 pins 5. when the frame frequency is 70 hz, and the output and cpu are without load and access respectively. (d0 to d15, a0 to a16, and /ube = gnd, and /cs, /oe, and /we = v cc2 ) 6. this is the resistance value between a y pin and a v pin (v 0 , v 1 , or v 2 ) when the load current (i on = 100 m a) is passed to a pin of y1 to y160.
24 m m m m pd16661a ac characteristics 1 display data transfer timing master mode (unless otherwise specified, v cc1 = 4.5 to 5.5 v, v cc2 = 3.0 to 3.6 v, v 0 = 0 v, v 1 = 1.4 to 2.0 v, v 2 = 2.8 to 4.0 v, t a = - - - - 20 to +70 c, frame frequency : 70 hz (f osc = 33.88 khz), output load : 100 pf) parameter symbol min. typ. max. unit remark stb clock cycle time t cyc 58 2/f osc m s stb high-level width t cwh 28 1/f osc m s stb low-level width t cwl 28 1/f osc m s stb rise time t r 100 ns stb fall time t f 100 ns stb - /frm delay time t psf 12 m s /frm - stb delay time t pfs 12 m s stb (output) /frm (output) t f t r t cwl t psf t psf t pfs t pfs t cwh t cyc 0.9 v cc1 0.1 v cc1 0.9 v cc1 0.1 v cc1
25 m m m m pd16661a slave mode (unless otherwise specified, v cc1 = 4.5 to 5.5 v, v cc2 = 3.0 to 3.6 v, v 0 = 0 v, v 1 = 1.4 to 2.0 v, v 2 = 2.8 to 4.0 v, t a = - - - - 20 to +70 c) parameter symbol min. typ. max. unit remark stb clock cycle time t cyc 10 m s stb high-level width t cwh 4 m s stb low-level width t cwl 4 m s stb rise time t r 150 ns stb fall time t f 150 ns /frm setup time t sfr 1 m s /frm hold time t hfr 1 m s stb (input) /frm (input) t f t r t cwl t sfr t sfr t hfr t hfr t cwh t cyc 0.7 v cc1 0.3 v cc1 0.7 v cc1 0.3 v cc1
26 m m m m pd16661a master/slave common items (unless otherwise specified, v cc1 = 4.5 to 5.5 v, v cc2 = 3.0 to 3.6 v, v 0 = 0 v, v 1 = 1.4 to 2.0 v, v 2 = 2.8 to 4.0 v, t a = - - - - 20 to +70 c) parameter symbol min. typ. max. unit remark output delay time (l1, l2, /dout) t dout1 50 100 ns output without load output delay time (y1 to y160) t dout2 90 150 ns output without load stb (output) y1 to y160 0.9 v 2 0.9 v 2 0.9 v cc1 0.9 v cc1 t dout2 t dout2 t dout1 t dout1 0.1 v 2 0.1 v 2 l1, l2, /dout
27 m m m m pd16661a ac characteristics 2 graphic access timing (unless otherwise specified, v cc1 = 4.5 to 5.5 v, v cc2 = 3.0 to 3.6 v, v 0 = 0 v, v 1 = 1.4 to 2.0 v, v 2 = 2.8 to 4.0 v, t a = - - - - 20 to +70 c, t r = t f = 5 ns, frame frequency : 70 hz (f osc = 33.88 khz)) parameter symbol min. typ. max. unit remark /oe,/we recovery time t ry 30 ns address setup time t as 10 ns address hold time t ah 20 ns rdy output delay time t ryr 30 ns c l = 15 pf rdy float time t ryz 30 ns note3 wait state time t ryw 35 ns note1 ready state time (without contention) t ryf1 60 100 ns note1 ready state time (with contention) t ryf2 650 1200 ns note1 data access time (read cycle) t acs 100 ns note2 data float time (read cycle) t hz 40 ns note3 /cs-/oe time (read cycle) t csoe 10 ns /oe-/cs time (read cycle) t oecs 20 ns write pulse width (write cycle) t wp 50 ns note1 data setup time (write cycle) t dw 20 ns data hold time (write cycle) t dh 20 ns /cs-/we time (write cycle) t cswe 10 ns /we-/cs time (write cycle) t wecs 20 ns reset pulse width t wres 100 ns rdy-/oe time t rdoe note4 rdy-/we time t rdwe note4 notes 1. load circuit 2. load circuit h h 1.0 k w 1.8 k w v cc2 60 pf 1.0 k w 1.8 k w v cc2 100 pf
28 m m m m pd16661a 3. load circuit 4. the display may be affected if there is a long time from the rise of rdy to the /oe or /we signals. it is recommended that t rdoe and t rdwe are 1000 ns or less. h 1.0 k w 1.8 k w v cc2 5 pf
29 m m m m pd16661a /oe,/we recovery time read cycle /oe,/we t ry 0.7 v cc2 0.3 v cc2 a16 to a0 /ube /cs /oe rdy d15 to d0 hi-z t ryr t ryf t ryw t hz t acs t csoe t as t ah t rdoe t oecs 0.1 v cc2 0.7 v cc2 0.7 v cc2 0.3 v cc2 0.3 v cc2 0.9 v cc2 0.1 v cc2 0.3 v cc2 output 0.1 v cc2 t ryz h
30 m m m m pd16661a write cycle reset pulse width /reset 0.3 v cc2 t wres h h a16 to a0 /ube /cs /we rdy d15 to d0 hi-z t ryr t ryf t ryw t dh t dw t wp t cswe t as t ah t rdwe t wecs 0.1 v cc2 0.7 v cc2 0.7 v cc2 0.3 v cc2 0.3 v cc2 0.7 v cc2 0.3 v cc2 0.3 v cc2 input t ryz 0.1 v cc2
31 m m m m pd16661a ac characteristics 3 cr oscillator (v cc2 = 3.0 to 3.6 v, t a = - - - - 20 to +70 c) parameter symbol min. typ. max. unit remark oscillation frequency f osc 32 36 40 khz external resistor 350 k w frame frequency ? 66.1 74.4 82.6 hz external resistor 350 k w 15. relationship between the oscillation , frame , and stb frequencies this relationship is as follows: frame frequency = oscillation frequency stb frequency = oscillation frequency 1 242 2 1 2
32 m m m m pd16661a 16. package drawing standard tcp package drawing ( m pd16661an-051) h japan japan d16661an-051 1 1 d16661an -051 (coating area) 6.8 13.8 10.2 flex resin 0.20.2 44.860.08 35 (slit) (36) (cut line) 18.5 18.5 20.01 0.12 p0.0815 f 1 cu max. 0.9 1.420.03 17.50.3 (sr) (coating area) 20.2 this product is face up type. this product is singleflex resin type. this flgure is shown by copper side over polyimide. detail see another sheet. 5 sprocket holes (23.75 mm) for 1 pattern. corner radius is 0.30 mm max. all tolerances unless otherwise specified 0.05 mm. specification basefilm : upilex-s adhesive : epoxy copper foil : electrolysis cu plating : sn solder resist : epoxy flex resin : polyimide coating resin : epoxy 75 m m 12 m m 25 m m min. 0.25 m m 25 m m 170.3 (sr) 170.3 (sr) 13 (hole) 13 (hole) 100.3 (sr) 100.3 (sr) 35 16.57 21.2 0 C4.6 17.50.3 (sr) 17 (mark) 17 (mark) 0.20.2 0 C4.6 p0.20.01x165 = 330.05 w0.10.015 4.750.03 1.075 1.2 2.375 2 4 5.625 (2.3) 10.2 (12.5) (cut line) (6.3) (cut line) 0.8 13 13.8 14.5 sr copper flex resin polyimide 6.8 (1.5) 4.20.2(sr) 2.60.2 (0.5) (0.4) 2.2 (1) (1) p0.1021 p0.1034 p0.0808 p0.450.01x73 = 32.850.045 w0.2250.02
33 m m m m pd16661a tcp tape winding direction from p.c. 18.5 0.2 r0.5 r0.8 f 1.2 1.6 r0.6 pi hole cu hole cu hole pi hole cu from p.c. 17 p0.2 20.01 0.3 0.4 (0.5) 0.3 0.2 0.3 0.2 0.3 0.2 0.4 0.06 0.10.015 0.60.015 0.40.015 0.60.015 14.5 13.8 10.2 (12.5) 0.40.015 from p.c. test pad and alignment mark details (x20) alignment hole details (x20) 1 f f cu output lead tape pull-out direction the cu pattern side is the underside of the tape. wind-up direction
34 m m m m pd16661a standard tcp package drawing ( m pd16661an-051) pin connection diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 nc v 0 v 1 v 2 v cc1 gnd v cc2 gnd a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 v cc2 osc1 osc2 gnd dir pl0 pl1 pl2 /refrh /reset /ube /cs /oe /we rdy /doff test bmode gmode ms v cc2 gnd /frm stb /dout l2 l1 v cc1 gnd v 2 v 1 v 0 nc nc nc nc y160 y159 y158 y157 y156 y155 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . y5 y4 y3 y2 y1 nc nc nc 1 2 3 4 5 6 7 8 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 160 161 162 163 164 165 166 die face up
35 m m m m pd16661a notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
m m m m pd16661a no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5 the application circuits and their parameters are for reference only and are not intended for use in actual design-ins.

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